For fifty years, a computer chip was built like a city with all its plumbing on the roof. Power lines and signal lines ran together in a stack of copper wiring laid down on top of the transistors, fighting for the same cramped space. As transistors shrank past the size of a virus, the fight got vicious. The power wires, squeezed thinnest, started bleeding voltage as heat before it ever reached the transistor. The signal wires had nowhere left to go.

The fix, now arriving in the most advanced chips on Earth, is almost crude in its simplicity: flip the wafer over and move all the power to the basement. Thin the silicon down to a few hundred nanometers, build a second layer of metal rails underneath the transistors, and feed power up through nano-scale vias drilled clean through the body of the chip. The front side, suddenly uncluttered, becomes a dedicated highway for signals. Engineers call it backside power delivery. It is the biggest change to how a chip is wired since the 1960s.

Intel has told the world, loudly, that it got there first. That part is true. What the patent record shows is stranger: the company built the smallest wall around the idea, and the company racing hardest to own it right now hasn’t operated a chip factory since 2015.

The number

US patent grants that describe backside power delivery or its core building block, the buried power rail, went from a single grant in 2016 to 80 in 2025. Another 46 have issued in the first half of 2026 alone. Across the whole window, 258 grants describe the technique.

Sort those grants by who owns them and the leaderboard does not match the press releases. Taiwan Semiconductor Manufacturing Company holds 87, far more than anyone. IBM holds 38. Samsung has 14. Arm, a company that designs chips but manufactures exactly none of them, holds 11. Intel holds 7. Count every spelling variant in Intel’s favor and the number climbs to about a dozen, still a rounding error next to TSMC’s pile.

This is the inversion worth sitting with. Intel will be the first company to ship backside power in high volume, on its 18A process, inside the Panther Lake laptop chips ramping this half. “We’re a node ahead of competitors in bringing backside power delivery to market,” Ben Sell, Intel’s VP of technology development, told reporters, and the benchmarks back him up: Intel’s own tests show the technique cutting platform voltage by about 30 percent and adding a 6 percent frequency gain. TSMC’s competing version, branded Super Power Rail, isn’t due in volume until late 2026 at the earliest, with most products in 2027. Samsung is later still.

So the company that will sell the first product holds the fewest patents, and the companies whose silicon arrives a year or two behind own the thicket. In an industry where patents are usually the leading indicator and products the lagging one, backside power runs the clock backward.

The idea was never Intel’s to begin with

To understand why, you have to leave Santa Clara and go to Leuven, Belgium, where a research consortium called imec quietly invents a decade of the semiconductor roadmap before any of its members will admit they need it. imec doesn’t sell chips. It runs a shared cleanroom where Intel, TSMC, Samsung, and Arm all park engineers and split the bill on problems none of them want to solve alone.

The buried power rail came out of that cleanroom. In 2018, imec researchers published a paper at the IEEE interconnect conference with the unglamorous title “High-Aspect-Ratio Ruthenium Lines for Buried Power Rail.” A year later, at the field’s marquee event, a team led by imec’s Julien Ryckaert laid out the full case in a paper called “Enabling Sub-5nm CMOS Technology Scaling Thinner and Taller!” It has been cited 81 times, a large number for a hardware-process paper, and it reads now like a blueprint everyone else followed. The same year, Arm’s engineers published their own study of how a CPU’s power network would have to be redrawn around buried rails. That early homework is visible in Arm’s 11 patents: a design house staking claims on an architecture it will never fabricate but every fab will have to license around.

Read the patents themselves and the shared engineering DNA is unmistakable, not a keyword coincidence. imec’s foundational grants describe the power network sitting “on the back side of the semiconductor substrate,” with through-silicon vias hauling current to the front. Intel’s key 2024 grant describes nanosheet transistor channels with “a backside power delivery line beneath” the source and drain structures, and signal lines, freed of power duty, packed at tighter pitch on the front. TSMC’s earliest, from 2020, claims a “backside power grid.” IBM’s newest, issued in September 2025, refines the plumbing with a “skip-level through-silicon via” that jumps past intermediate metal layers to cut resistance. Different companies, same physical move: lift the power out of the attic and bolt it to the floor.

One detail from that first imec paper deserves to be dragged into the light, because it has a supply-chain tail. You cannot make a buried power rail out of copper. Copper poisons silicon and needs a barrier liner that, at these dimensions, eats the whole wire. So the rails are cut from tungsten or ruthenium, refractory metals that survive the brutal heat of front-end processing. Ruthenium is a platinum-group metal, scarce and mostly a byproduct of other mining. The decision to wire the power layer of every leading-edge chip in ruthenium was made, in effect, in a Belgian lab in 2018, and the metals desks haven’t fully priced in what happens when three foundries need it at scale.

The fab-less company building the biggest wall

Then there is IBM, which is the real surprise on the leaderboard. IBM sold its chip-manufacturing business to GlobalFoundries in 2015 in a deal so lopsided it paid GlobalFoundries 1.5 billion dollars to take the fabs off its hands. A decade later, IBM owns no leading-edge factory. It also owns 38 backside-power grants, and 20 of them, more than half, have issued since January 2025. No other company on the list is accelerating that hard right now.

What IBM kept when it sold the fabs was the research lab in Albany, New York, and the lab never stopped inventing the transistor. The nanosheet architecture that TSMC, Samsung, and Intel are all now shipping traces back to IBM demonstrations from Albany. Backside power is the same pattern: invent it in the lab, patent it, and feed it to partners who do own factories. IBM’s partners are Samsung and, increasingly, Japan’s state-backed startup Rapidus. That arrangement is contentious enough that GlobalFoundries sued IBM in 2023, alleging it had funneled trade secrets to Rapidus; the two settled in January 2026. The lawsuit is a tell. IBM’s patents aren’t defensive scraps. They are the asset, the only chip-making asset a company without a chip factory has left.

Who cares

For anyone deciding where the real chokepoints sit in the AI hardware stack, the gap between Intel’s product lead and its patent position is the whole story. Backside power isn’t optional. Every advanced logic chip, the parts that train and run large models, will use it within three years, because the alternative is leaving performance and efficiency on the table that no one designing a data center can afford. When a capability becomes mandatory, the question stops being who ships first and becomes who collects rent. Intel may win the first lap and still pay royalties to run the race, to a Belgian consortium that licenses the foundational work, to a New York research lab with no factory, and to the Taiwanese foundry that out-filed everyone while its own product was still two years out.

The chip that finally separated power from signal separated something else too: the company that builds the thing from the companies that own the idea of it. In semiconductors, those used to be one and the same. The basement wiring is where they came apart.

Method note. Counts come from 9.3M US utility patent grants sourced from USPTO bulk grant XML, filtered to grants whose text describes “backside power” or the “buried power rail,” issued from 2016 through mid-June 2026. Assignee totals combine variant spellings and subsidiary names for each company; the same keyword filter was applied to every assignee, so cross-company comparisons are like-for-like. Counting Intel’s every phrasing variant raises its total from 7 to about 12, which does not change the ranking. Origin and citation data for the foundational imec and Arm papers are from OpenAlex. Product timelines, performance figures, and corporate history are drawn from Intel, TSMC, and imec technical disclosures and from reporting by IEEE Spectrum, Tom’s Hardware, Semiconductor Engineering, and TrendForce. Patent counts are a measure of disclosed invention, not of manufacturing capability or product readiness, which is precisely the gap this piece is about.